Negative edge triggered flip flop circuit

How Asynchronous 3-bit up down counter construct?ДЄs we know that in the up-counter each flip-flop is triggered by the normal output of the preceding flip-flop (from output Q of first flip-flop to clock of next flip-flop) whereas in a down-counter, each flip-flop is triggered by the complement output of the preceding flip-flop (from output Q^ of first flip-flop to clock of next flip-flop). And from new truth table, we have to design new circuit by karnaugh Map technique. Now question is how can we do that? We place both counterвЂ™s truth table then combine them. For that we have to go through some process. We have to make it by combine both Up-Counter and Down Counter. Hence the count sequences goes on decreasing from 7, 6, 5, 4, 3, 2, 1, 0, 7, and so on with each clock pulse. Similarly, with each negative transition of the output Q 0, the output Q 1 toggles and the same thing happens for Q 2, also. With each negative edge of the clock Q 0 toggles its state. The starting count sequence is QвЂІ 2QвЂІ 1QвЂІ 0 = 111. Looks at bellow and mind it, only the outputs of the counter may be taken from the complement outputs of the flip-flops, i.e., QвЂІ, rather than from the normal outputs for each flip-flop as shown in circuit Since the outputs are taken from the complements of the flip-flops. First we look on the truth table of that it will help us to understand the working principal of down counter. What is down counter? A down-counter using n number of flip-flops, counts downward starting from a maximum count of (2n вЂ“ 1) to zero. I request you please read that to complete discussion. In my previous post on ripple counter we already saw the working principle of up-counter. Every steps it count upper value from lower. How Asynchronous 3-bit up down counter construct?.Some questions we have to clear during the post. Here we come with asynchronous 3-bit up down counter.